module JWDatapath(Clk, Rst);
input Clk, Rst;


wire [31:0]PC;
wire [31:0]Instruction;

wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite;
wire ZeroDetect;

//Fetch
InstructionMemory Im(PC, Instruction, Clk, Rst);

//PC

wire [31:0]PCp4, PCin;
Register_32bit PCC(Clk, Rst, PCin, PC, {Rst, Rst}); 

Adder_32bit PCp(PC, 32'h0004, PCp4);

wire [31:0]JumpAddress;
assign JumpAddress = {PCp4[31:28], Instruction[25:0], 2'b00};

wire [31:0]Branchaa;
Adder_32bit brancha(PCp4, {Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15], Instruction[15:0], 2'b00}, Branchaa);

wire beq;
and begtest(beq, Branch, ZeroDetect);
wire [31:0]Jumping;
MUX2to1_32bit branchaaa(PCp4, Branchaa, Jumping, beq);
MUX2to1_32bit jumpaaa(Jumping, JumpAddress, PCin, Jump);



//control

wire [2:0]ALUOp1, ALUOp;
Control Cont(Instruction[31:26], RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp1, MemWrite, ALUSrc, RegWrite);
ALUcontrol ALUC(ALUOp1, Instruction[5:0], ALUOp);

//Register File
wire [4:0]WriteRegister;
wire [7:0]ReadData1, ReadData2;
wire [7:0]WriteData;
MUX2to1_5bit WR(Instruction[20:16], Instruction[15:11], WriteRegister, RegDst);
RegisterFile RF(Instruction[25:21], Instruction[20:16], WriteRegister, WriteData, ReadData1, ReadData2, RegWrite, Clk, Rst); 

//ALU
wire [7:0]ALUin2;
wire [7:0]ALUresult;
MUX2to1_8bit ALUin(ReadData2, Instruction[7:0], ALUin2, ALUSrc);
ALU_8bit Alu1(ReadData1, ALUin2, ALUresult, ALUOp, ZeroDetect);

//DataMemory
wire [7:0]DataOut;
DataMemory DM(ALUresult, ReadData2, DataOut, MemWrite, MemRead, Clk, Rst);

MUX2to1_8bit Wb(ALUresult, DataOut, WriteData, MemtoReg);



endmodule


//Control Unit START

module Control(
  Instruction,
  RegDst,
  Jump,
  Branch,
  MemRead,
  MemtoReg,
  ALUOp,
  MemWrite,
  ALUSrc,
  RegWrite
);
input [5:0]Instruction;
output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite;
output [2:0]ALUOp;


and regdst(RegDst, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

wire RegWrite1, RegWrite2, RegWrite3;
and regwrite1(RegWrite1, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);
and regwrite2(RegWrite2, ~Instruction[3], ~Instruction[4], Instruction[5]);
and regwrite3(RegWrite3, Instruction[0], ~Instruction[1], Instruction[2], Instruction[3], ~Instruction[4], ~Instruction[5]);
or regwrite(RegWrite, RegWrite1, RegWrite2);

nand alusrc(ALUSrc, ~Instruction[0], ~Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

and memwrite(MemWrite, Instruction[0], Instruction[1], ~Instruction[2], Instruction[3], ~Instruction[4], Instruction[5]);

and memread(MemRead, Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

and memtoreg(MemtoReg, Instruction[0], Instruction[1], ~Instruction[2], ~Instruction[3], ~Instruction[4], Instruction[5]);

and branch(Branch, ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);

and jump(Jump, ~Instruction[0], Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);


wire lwswt, orit;
and lwt(lwswt, ~Instruction[4], Instruction[5]);
and ort(orit, ~Instruction[0], ~Instruction[1], Instruction[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);


and aluopt2(ALUOp[2], ~Instruction[3], ~Instruction[4], ~Instruction[5]);
or aluopt1(ALUOp[1], lwswt, orit);
and aluopt0(ALUOp[0], Instruction[0], ~Instruction[1]);




endmodule

module ALUcontrol(
  ALUOp,
  Instruction,
  ALUcon
);

input [2:0]ALUOp;
input [5:0]Instruction;
output [2:0]ALUcon;

wire [2:0]ALUOpt;
wire ALUOptt;
or ALUOPtt0(ALUOptt, Instruction[0], Instruction[3]);
 

and ALUOpt0(ALUOpt[0], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ALUOptt);
and ALUOpt1(ALUOpt[1], ~ALUOp[0], ~ALUOp[1], ALUOp[2], ~Instruction[2]);
and ALUOpt2(ALUOpt[2], ~ALUOp[0], ~ALUOp[1], ALUOp[2], Instruction[1]);

MUX8to1_1bit output0(1'b0, 1'b1, 1'b0, 1'b0, ALUOpt[0], 1'b0, 1'b0, 1'b0, ALUcon[0], ALUOp, 1'b1);
MUX8to1_1bit output1(1'b0, 1'b0, 1'b1, 1'b0, ALUOpt[1], 1'b0, 1'b1, 1'b0, ALUcon[1], ALUOp, 1'b1);
MUX8to1_1bit output2(1'b0, 1'b0, 1'b0, 1'b0, ALUOpt[2], 1'b0, 1'b1, 1'b0, ALUcon[2], ALUOp, 1'b1);


endmodule



//Control Unit END


//RegisterFile START

module RegisterFile(
  ReadRegister1,
  ReadRegister2,
  WriteRegister,
  WriteData,
  ReadData1,
  ReadData2,
  RegWrite,
  clk,
  rst
);

input [4:0]ReadRegister1, ReadRegister2, WriteRegister;
input [7:0]WriteData;
input RegWrite;
input clk, rst;
output [7:0]ReadData1, ReadData2;

//register setting
wire [7:0]regout0, regout1, regout2, regout3, regout4, regout5, regout6, regout7,
          regout8, regout9, regout10, regout11, regout12, regout13, regout14, regout15,
  	       regout16, regout17, regout18, regout19, regout20, regout21, regout22, regout23,
          regout24, regout25, regout26, regout27, regout28, regout29, regout30, regout31;

//WriteData

wire [31:0]realwrite, tempwrite;
DEC5to32 dec1(WriteRegister, tempwrite);

and rw0(realwrite[0], RegWrite, tempwrite[0]);
and rw1(realwrite[1], RegWrite, tempwrite[1]);
and rw2(realwrite[2], RegWrite, tempwrite[2]);
and rw3(realwrite[3], RegWrite, tempwrite[3]);
and rw4(realwrite[4], RegWrite, tempwrite[4]);
and rw5(realwrite[5], RegWrite, tempwrite[5]);
and rw6(realwrite[6], RegWrite, tempwrite[6]);
and rw7(realwrite[7], RegWrite, tempwrite[7]);
and rw8(realwrite[8], RegWrite, tempwrite[8]);
and rw9(realwrite[9], RegWrite, tempwrite[9]);
and rw10(realwrite[10], RegWrite, tempwrite[10]);
and rw11(realwrite[11], RegWrite, tempwrite[11]);
and rw12(realwrite[12], RegWrite, tempwrite[12]);
and rw13(realwrite[13], RegWrite, tempwrite[13]);
and rw14(realwrite[14], RegWrite, tempwrite[14]);
and rw15(realwrite[15], RegWrite, tempwrite[15]);
and rw16(realwrite[16], RegWrite, tempwrite[16]);
and rw17(realwrite[17], RegWrite, tempwrite[17]);
and rw18(realwrite[18], RegWrite, tempwrite[18]);
and rw19(realwrite[19], RegWrite, tempwrite[19]);
and rw20(realwrite[20], RegWrite, tempwrite[20]);
and rw21(realwrite[21], RegWrite, tempwrite[21]);
and rw22(realwrite[22], RegWrite, tempwrite[22]);
and rw23(realwrite[23], RegWrite, tempwrite[23]);
and rw24(realwrite[24], RegWrite, tempwrite[24]);
and rw25(realwrite[25], RegWrite, tempwrite[25]);
and rw26(realwrite[26], RegWrite, tempwrite[26]);
and rw27(realwrite[27], RegWrite, tempwrite[27]);
and rw28(realwrite[28], RegWrite, tempwrite[28]);
and rw29(realwrite[29], RegWrite, tempwrite[29]);
and rw30(realwrite[30], RegWrite, tempwrite[30]);
and rw31(realwrite[31], RegWrite, tempwrite[31]);



//$zero
Register_8bit R0(clk, rst, 8'b00000000, regout0, 2'b11);
//$at
Register_8bit R1(clk, rst, WriteData, regout1, {realwrite[1], realwrite[1]});
//$v0~$v1
Register_8bit R2(clk, rst, WriteData, regout2, {realwrite[2], realwrite[2]});
Register_8bit R3(clk, rst, WriteData, regout3, {realwrite[3], realwrite[3]});
//$a0~$a3
Register_8bit R4(clk, rst, WriteData, regout4, {realwrite[4], realwrite[4]});
Register_8bit R5(clk, rst, WriteData, regout5, {realwrite[5], realwrite[5]});
Register_8bit R6(clk, rst, WriteData, regout6, {realwrite[6], realwrite[6]});
Register_8bit R7(clk, rst, WriteData, regout7, {realwrite[7], realwrite[7]});
//$t0~$t7
Register_8bit R8(clk, rst, WriteData, regout8, {realwrite[8], realwrite[8]});
Register_8bit R9(clk, rst, WriteData, regout9, {realwrite[9], realwrite[9]});
Register_8bit R10(clk, rst, WriteData, regout10, {realwrite[10], realwrite[10]});
Register_8bit R11(clk, rst, WriteData, regout11, {realwrite[11], realwrite[11]});
Register_8bit R12(clk, rst, WriteData, regout12, {realwrite[12], realwrite[12]});
Register_8bit R13(clk, rst, WriteData, regout13, {realwrite[13], realwrite[13]});
Register_8bit R14(clk, rst, WriteData, regout14, {realwrite[14], realwrite[14]});
Register_8bit R15(clk, rst, WriteData, regout15, {realwrite[15], realwrite[15]});
//$s0~$s7
Register_8bit R16(clk, rst, WriteData, regout16, {realwrite[16], realwrite[16]});
Register_8bit R17(clk, rst, WriteData, regout17, {realwrite[17], realwrite[17]});
Register_8bit R18(clk, rst, WriteData, regout18, {realwrite[18], realwrite[18]});
Register_8bit R19(clk, rst, WriteData, regout19, {realwrite[19], realwrite[19]});
Register_8bit R20(clk, rst, WriteData, regout20, {realwrite[20], realwrite[20]});
Register_8bit R21(clk, rst, WriteData, regout21, {realwrite[21], realwrite[21]});
Register_8bit R22(clk, rst, WriteData, regout22, {realwrite[22], realwrite[22]});
Register_8bit R23(clk, rst, WriteData, regout23, {realwrite[23], realwrite[23]});
//$t8~$t9
Register_8bit R24(clk, rst, WriteData, regout24, {realwrite[24], realwrite[24]});
Register_8bit R25(clk, rst, WriteData, regout25, {realwrite[25], realwrite[25]});
//$k0~$k1
Register_8bit R26(clk, rst, WriteData, regout26, {realwrite[26], realwrite[26]});
Register_8bit R27(clk, rst, WriteData, regout27, {realwrite[27], realwrite[27]});
//$gp
Register_8bit R28(clk, rst, WriteData, regout28, {realwrite[28], realwrite[28]});
//$sp
Register_8bit R29(clk, rst, WriteData, regout29, {realwrite[29], realwrite[29]});
//$fp
Register_8bit R30(clk, rst, WriteData, regout30, {realwrite[30], realwrite[30]});
//$ra
Register_8bit R31(clk, rst, WriteData, regout31, {realwrite[31], realwrite[31]});
  
  
           
//ReadData1
MUX32to1_8bit RD1(regout0, regout1, regout2, regout3, regout4, regout5, regout6, regout7, regout8, regout9, regout10, regout11, regout12, regout13, regout14, regout15, regout16, regout17, regout18, regout19, regout20, regout21, regout22, regout23, regout24, regout25, regout26, regout27, regout28, regout29, regout30, regout31, ReadData1, ReadRegister1);
//ReadData2
MUX32to1_8bit RD2(regout0, regout1, regout2, regout3, regout4, regout5, regout6, regout7, regout8, regout9, regout10, regout11, regout12, regout13, regout14, regout15, regout16, regout17, regout18, regout19, regout20, regout21, regout22, regout23, regout24, regout25, regout26, regout27, regout28, regout29, regout30, regout31, ReadData2, ReadRegister2);





endmodule

//RegisterFile END

//InstructionMemory START

module InstructionMemory(PC, Instruction, clk, rst);

input clk, rst;
input [31:0]PC;
output [31:0]Instruction;

wire [31:0]inst0, inst1, inst2, inst3, inst4, inst5, inst6, inst7, inst8, inst9, inst10, inst11, inst12, inst13, inst14, inst15, inst16, inst17, inst18, inst19, inst20, inst21, inst22, inst23, inst24, inst25, inst26, inst27, inst28, inst29, inst30, inst31;
wire [31:0]ins0, ins1, ins2, ins3, ins4, ins5, ins6, ins7, ins8, ins9, ins10, ins11, ins12, ins13, ins14, ins15, ins16, ins17, ins18, ins19, ins20, ins21, ins22, ins23, ins24, ins25, ins26, ins27, ins28, ins29, ins30, ins31;  


assign inst0 = 32'b00110101000010000000000000000001;
assign inst1 = 32'b00110101001010010000000000000100;
assign inst2 = 32'b00110101010010100000000000010000;
assign inst3 = 32'b00010010000010100000000000100000;
assign inst4 = 32'b00000010000100000100000000100000;
assign inst5 = 32'b10101101011100000000000000000100;
assign inst6 = 32'b00000001011010110100100000100000;
assign inst7 = 32'b00001000000000000000000000001100;
assign inst8 = 32'b00000010000100000000000000100100;
assign inst9 = 32'b00010010000010100000000000110100;
assign inst10 = 32'b00000010000100000100000000100000;
assign inst11 = 32'b00000010001100011000000000100000;
assign inst12 = 32'b00001000000000000000000000100100;
assign inst13 = 32'b10101101011100010000000000000100;


Register_32bit Reg0(clk, rst, inst0, ins0, 2'b11);
Register_32bit Reg1(clk, rst, inst1, ins1, 2'b11);
Register_32bit Reg2(clk, rst, inst2, ins2, 2'b11);
Register_32bit Reg3(clk, rst, inst3, ins3, 2'b11);
Register_32bit Reg4(clk, rst, inst4, ins4, 2'b11);
Register_32bit Reg5(clk, rst, inst5, ins5, 2'b11);
Register_32bit Reg6(clk, rst, inst6, ins6, 2'b11);
Register_32bit Reg7(clk, rst, inst7, ins7, 2'b11);
Register_32bit Reg8(clk, rst, inst8, ins8, 2'b11);
Register_32bit Reg9(clk, rst, inst9, ins9, 2'b11);
Register_32bit Reg10(clk, rst, inst10, ins10, 2'b11);
Register_32bit Reg11(clk, rst, inst11, ins11, 2'b11);
Register_32bit Reg12(clk, rst, inst12, ins12, 2'b11);
Register_32bit Reg13(clk, rst, inst13, ins13, 2'b11);
Register_32bit Reg14(clk, rst, inst14, ins14, 2'b11);
Register_32bit Reg15(clk, rst, inst15, ins15, 2'b11);
Register_32bit Reg16(clk, rst, inst16, ins16, 2'b11);
Register_32bit Reg17(clk, rst, inst17, ins17, 2'b11);
Register_32bit Reg18(clk, rst, inst18, ins18, 2'b11);
Register_32bit Reg19(clk, rst, inst19, ins19, 2'b11);
Register_32bit Reg20(clk, rst, inst20, ins20, 2'b11);
Register_32bit Reg21(clk, rst, inst21, ins21, 2'b11);
Register_32bit Reg22(clk, rst, inst22, ins22, 2'b11);
Register_32bit Reg23(clk, rst, inst23, ins23, 2'b11);
Register_32bit Reg24(clk, rst, inst24, ins24, 2'b11);
Register_32bit Reg25(clk, rst, inst25, ins25, 2'b11);
Register_32bit Reg26(clk, rst, inst26, ins26, 2'b11);
Register_32bit Reg27(clk, rst, inst27, ins27, 2'b11);
Register_32bit Reg28(clk, rst, inst28, ins28, 2'b11);
Register_32bit Reg29(clk, rst, inst29, ins29, 2'b11);
Register_32bit Reg30(clk, rst, inst30, ins30, 2'b11);
Register_32bit Reg31(clk, rst, inst31, ins31, 2'b11);



MUX32to1_32bit m0(ins0, ins1, ins2, ins3, ins4, ins5, ins6, ins7, ins8, ins9, ins10, ins11, ins12, ins13, ins14, ins15, ins16, ins17, ins18, ins19, ins20, ins21, ins22, ins23, ins24, ins25, ins26, ins27, ins28, ins29, ins30, ins31, Instruction, PC[6:2]);

endmodule

//InstructionMemory END

//DataMemory START

module DataMemory(address_in,data_in,data_out,Sel_W,Sel_R,clk,rst);

input [7:0] address_in;
input [7:0] data_in;
input Sel_W;  //1->write
input Sel_R;  //1->read	
output [7:0] data_out;

input clk;
input rst;

wire [7:0] ro1,ro2,ro3,ro4,ro5,ro6,ro7,ro8,
	   ro9,ro10,ro11,ro12,ro13,ro14,ro15,ro16,
	   ro17,ro18,ro19,ro20,ro21,ro22,ro23,ro24,
	   ro25,ro26,ro27,ro28,ro29,ro30,ro31,ro32;

wire [31:0]tempwrite, realwrite;
DEC5to32 dec1(address_in[4:0], tempwrite);
and rw0(realwrite[0], Sel_W, tempwrite[0]);
and rw1(realwrite[1], Sel_W, tempwrite[1]);
and rw2(realwrite[2], Sel_W, tempwrite[2]);
and rw3(realwrite[3], Sel_W, tempwrite[3]);
and rw4(realwrite[4], Sel_W, tempwrite[4]);
and rw5(realwrite[5], Sel_W, tempwrite[5]);
and rw6(realwrite[6], Sel_W, tempwrite[6]);
and rw7(realwrite[7], Sel_W, tempwrite[7]);
and rw8(realwrite[8], Sel_W, tempwrite[8]);
and rw9(realwrite[9], Sel_W, tempwrite[9]);
and rw10(realwrite[10], Sel_We, tempwrite[10]);
and rw11(realwrite[11], Sel_W, tempwrite[11]);
and rw12(realwrite[12], Sel_W, tempwrite[12]);
and rw13(realwrite[13], Sel_W, tempwrite[13]);
and rw14(realwrite[14], Sel_W, tempwrite[14]);
and rw15(realwrite[15], Sel_W, tempwrite[15]);
and rw16(realwrite[16], Sel_W, tempwrite[16]);
and rw17(realwrite[17], Sel_W, tempwrite[17]);
and rw18(realwrite[18], Sel_W, tempwrite[18]);
and rw19(realwrite[19], Sel_W, tempwrite[19]);
and rw20(realwrite[20], Sel_W, tempwrite[20]);
and rw21(realwrite[21], Sel_W, tempwrite[21]);
and rw22(realwrite[22], Sel_W, tempwrite[22]);
and rw23(realwrite[23], Sel_W, tempwrite[23]);
and rw24(realwrite[24], Sel_W, tempwrite[24]);
and rw25(realwrite[25], Sel_W, tempwrite[25]);
and rw26(realwrite[26], Sel_W, tempwrite[26]);
and rw27(realwrite[27], Sel_W, tempwrite[27]);
and rw28(realwrite[28], Sel_W, tempwrite[28]);
and rw29(realwrite[29], Sel_W, tempwrite[29]);
and rw30(realwrite[30], Sel_W, tempwrite[30]);
and rw31(realwrite[31], Sel_W, tempwrite[31]);


Register_8bit rr1(clk,rst,data_in,ro1,{realwrite[0], realwrite[0]});
Register_8bit rr2(clk,rst,data_in,ro2,{realwrite[1], realwrite[1]});
Register_8bit rr3(clk,rst,data_in,ro3,{realwrite[2], realwrite[2]});
Register_8bit rr4(clk,rst,data_in,ro4,{realwrite[3], realwrite[3]});
Register_8bit rr5(clk,rst,data_in,ro5,{realwrite[4], realwrite[4]});
Register_8bit rr6(clk,rst,data_in,ro6,{realwrite[5], realwrite[5]});
Register_8bit rr7(clk,rst,data_in,ro7,{realwrite[6], realwrite[6]});
Register_8bit rr8(clk,rst,data_in,ro8,{realwrite[7], realwrite[7]});
Register_8bit rr9(clk,rst,data_in,ro9,{realwrite[8], realwrite[8]});
Register_8bit rr10(clk,rst,data_in,ro10,{realwrite[9], realwrite[9]});
Register_8bit rr11(clk,rst,data_in,ro11,{realwrite[10], realwrite[10]});
Register_8bit rr12(clk,rst,data_in,ro12,{realwrite[11], realwrite[11]});
Register_8bit rr13(clk,rst,data_in,ro13,{realwrite[12], realwrite[12]});
Register_8bit rr14(clk,rst,data_in,ro14,{realwrite[13], realwrite[13]});
Register_8bit rr15(clk,rst,data_in,ro15,{realwrite[14], realwrite[14]});
Register_8bit rr16(clk,rst,data_in,ro16,{realwrite[15], realwrite[15]});
Register_8bit rr17(clk,rst,data_in,ro17,{realwrite[16], realwrite[16]});
Register_8bit rr18(clk,rst,data_in,ro18,{realwrite[17], realwrite[17]});
Register_8bit rr19(clk,rst,data_in,ro19,{realwrite[18], realwrite[18]});
Register_8bit rr20(clk,rst,data_in,ro20,{realwrite[19], realwrite[19]});
Register_8bit rr21(clk,rst,data_in,ro21,{realwrite[20], realwrite[20]});
Register_8bit rr22(clk,rst,data_in,ro22,{realwrite[21], realwrite[21]});
Register_8bit rr23(clk,rst,data_in,ro23,{realwrite[22], realwrite[22]});
Register_8bit rr24(clk,rst,data_in,ro24,{realwrite[23], realwrite[23]});
Register_8bit rr25(clk,rst,data_in,ro25,{realwrite[24], realwrite[24]});
Register_8bit rr26(clk,rst,data_in,ro26,{realwrite[25], realwrite[25]});
Register_8bit rr27(clk,rst,data_in,ro27,{realwrite[26], realwrite[26]});
Register_8bit rr28(clk,rst,data_in,ro28,{realwrite[27], realwrite[27]});
Register_8bit rr29(clk,rst,data_in,ro29,{realwrite[28], realwrite[28]});
Register_8bit rr30(clk,rst,data_in,ro30,{realwrite[29], realwrite[29]});
Register_8bit rr31(clk,rst,data_in,ro31,{realwrite[30], realwrite[30]});
Register_8bit rr32(clk,rst,data_in,ro32,{realwrite[31], realwrite[31]});

MUX32to1_8bit mm1(ro1,ro2,ro3,ro4,ro5,ro6,ro7,ro8,
	          ro9,ro10,ro11,ro12,ro13,ro14,ro15,ro16,
	          ro17,ro18,ro19,ro20,ro21,ro22,ro23,ro24,
	          ro25,ro26,ro27,ro28,ro29,ro30,ro31,ro32,
	          data_out,address_in[4:0]);


endmodule



//DataMemory END

//ALU START

module ALU_8bit(A, B, S, CU, Z);
  input [7:0] A, B;
  input [2:0] CU;
  input Z;
  output [7:0] S;
  wire [7:0] wS1, wS2, wS3, wS4;
  
  and a1(wS1[0], A[0], B[0]);
  and a2(wS1[1], A[1], B[1]);
  and a3(wS1[2], A[2], B[2]);
  and a4(wS1[3], A[3], B[3]);
  and a5(wS1[4], A[4], B[4]);
  and a6(wS1[5], A[5], B[5]);
  and a7(wS1[6], A[6], B[6]);
  and a8(wS1[7], A[7], B[7]);
  
  or o1(wS2[0], A[0], B[0]);
  or o2(wS2[1], A[1], B[1]);
  or o3(wS2[2], A[2], B[2]);
  or o4(wS2[3], A[3], B[3]);
  or o5(wS2[4], A[4], B[4]);
  or o6(wS2[5], A[5], B[5]);
  or o7(wS2[6], A[6], B[6]);
  or o8(wS2[7], A[7], B[7]);
  
  wire overflow, carryout;
  AdderSubtracter AS1(A, B, wS3, overflow, carryout, CU[2]);
  Slt SL1(A, B, wS4);
  
  MUX8to1_8bit OUT(wS1, wS2, wS3, 8'b00000000, 8'b00000000, 8'b00000000, wS3, wS4, S, CU);
  
  and zerodetect(Z, ~S[0], ~S[1], ~S[2], ~S[3], ~S[4], ~S[5], ~S[6], ~S[7]); 
  
  endmodule
  
//ALU END

//MUX START

module MUX2to1_1bit(
  input0,
  input1,
  output0,
  sel,
  on
);
input input0, input1;
input sel, on;
output output0;

wire output1, output2;
and a1(output1, input0, ~sel);
and a2(output2, input1, sel);

or o1(output0, output1, output2);

endmodule

module MUX2to1_5bit(
  input0,
  input1,
  output0,
  sel
);

input [4:0]input0, input1;
input sel;
output [4:0]output0;

MUX2to1_1bit m0(input0[0], input1[0], output0[0], sel, 1'b1);
MUX2to1_1bit m1(input0[1], input1[1], output0[1], sel, 1'b1);
MUX2to1_1bit m2(input0[2], input1[2], output0[2], sel, 1'b1);
MUX2to1_1bit m3(input0[3], input1[3], output0[3], sel, 1'b1);
MUX2to1_1bit m4(input0[4], input1[4], output0[4], sel, 1'b1);


endmodule

module MUX2to1_8bit(
  input0,
  input1,
  output0,
  sel
);

input [7:0]input0, input1;
input sel;
output [7:0]output0;

MUX2to1_1bit m0(input0[0], input1[0], output0[0], sel, 1'b1);
MUX2to1_1bit m1(input0[1], input1[1], output0[1], sel, 1'b1);
MUX2to1_1bit m2(input0[2], input1[2], output0[2], sel, 1'b1);
MUX2to1_1bit m3(input0[3], input1[3], output0[3], sel, 1'b1);
MUX2to1_1bit m4(input0[4], input1[4], output0[4], sel, 1'b1);
MUX2to1_1bit m5(input0[5], input1[5], output0[5], sel, 1'b1);
MUX2to1_1bit m6(input0[6], input1[6], output0[6], sel, 1'b1);
MUX2to1_1bit m7(input0[7], input1[7], output0[7], sel, 1'b1);

endmodule

module MUX2to1_32bit(
  input0,
  input1,
  output0,
  sel
);

input [31:0]input0, input1;
input sel;
output [31:0]output0;

MUX2to1_1bit m0(input0[0], input1[0], output0[0], sel, 1'b1);
MUX2to1_1bit m1(input0[1], input1[1], output0[1], sel, 1'b1);
MUX2to1_1bit m2(input0[2], input1[2], output0[2], sel, 1'b1);
MUX2to1_1bit m3(input0[3], input1[3], output0[3], sel, 1'b1);
MUX2to1_1bit m4(input0[4], input1[4], output0[4], sel, 1'b1);
MUX2to1_1bit m5(input0[5], input1[5], output0[5], sel, 1'b1);
MUX2to1_1bit m6(input0[6], input1[6], output0[6], sel, 1'b1);
MUX2to1_1bit m7(input0[7], input1[7], output0[7], sel, 1'b1);
MUX2to1_1bit m8(input0[8], input1[8], output0[8], sel, 1'b1);
MUX2to1_1bit m9(input0[9], input1[9], output0[9], sel, 1'b1);
MUX2to1_1bit m10(input0[10], input1[10], output0[10], sel, 1'b1);
MUX2to1_1bit m11(input0[11], input1[11], output0[11], sel, 1'b1);
MUX2to1_1bit m12(input0[12], input1[12], output0[12], sel, 1'b1);
MUX2to1_1bit m13(input0[13], input1[13], output0[13], sel, 1'b1);
MUX2to1_1bit m14(input0[14], input1[14], output0[14], sel, 1'b1);
MUX2to1_1bit m15(input0[15], input1[15], output0[15], sel, 1'b1);
MUX2to1_1bit m16(input0[16], input1[16], output0[16], sel, 1'b1);
MUX2to1_1bit m17(input0[17], input1[17], output0[17], sel, 1'b1);
MUX2to1_1bit m18(input0[18], input1[18], output0[18], sel, 1'b1);
MUX2to1_1bit m19(input0[19], input1[19], output0[19], sel, 1'b1);
MUX2to1_1bit m20(input0[20], input1[20], output0[20], sel, 1'b1);
MUX2to1_1bit m21(input0[21], input1[21], output0[21], sel, 1'b1);
MUX2to1_1bit m22(input0[22], input1[22], output0[22], sel, 1'b1);
MUX2to1_1bit m23(input0[23], input1[23], output0[23], sel, 1'b1);
MUX2to1_1bit m24(input0[24], input1[24], output0[24], sel, 1'b1);
MUX2to1_1bit m25(input0[25], input1[25], output0[25], sel, 1'b1);
MUX2to1_1bit m26(input0[26], input1[26], output0[26], sel, 1'b1);
MUX2to1_1bit m27(input0[27], input1[27], output0[27], sel, 1'b1);
MUX2to1_1bit m28(input0[28], input1[28], output0[28], sel, 1'b1);
MUX2to1_1bit m29(input0[29], input1[29], output0[29], sel, 1'b1);
MUX2to1_1bit m30(input0[30], input1[30], output0[30], sel, 1'b1);
MUX2to1_1bit m31(input0[31], input1[31], output0[31], sel, 1'b1);




endmodule

module MUX4to1_1bit(
  input0,
  input1,
  input2,
  input3,
  output0,
  sel,
  on
);

input input0, 
      input1,
      input2,
      input3;
input [1:0]sel;
input on;
output output0;

wire [3:0]w1;

and a0(w1[0], input0, ~sel[0], ~sel[1], on);
and a1(w1[1], input1, sel[0], ~sel[1], on);
and a2(w1[2], input2, ~sel[0], sel[1], on);
and a3(w1[3], input3, sel[0], sel[1], on);

or o0(output0, w1[0], w1[1], w1[2], w1[3]);

endmodule

module MUX4to1_8bit(
  input0,
  input1,
  input2,
  input3,
  output0,
  sel
);

input [7:0]input0, input1, input2, input3;
input [1:0]sel;
output [7:0]output0;

MUX4to1_1bit m0(input0[0], input1[0], input2[0], input3[0], output0[0], sel, 1'b1);
MUX4to1_1bit m1(input0[1], input1[1], input2[1], input3[1], output0[1], sel, 1'b1);
MUX4to1_1bit m2(input0[2], input1[2], input2[2], input3[2], output0[2], sel, 1'b1);
MUX4to1_1bit m3(input0[3], input1[3], input2[3], input3[3], output0[3], sel, 1'b1);
MUX4to1_1bit m4(input0[4], input1[4], input2[4], input3[4], output0[4], sel, 1'b1);
MUX4to1_1bit m5(input0[5], input1[5], input2[5], input3[5], output0[5], sel, 1'b1);
MUX4to1_1bit m6(input0[6], input1[6], input2[6], input3[6], output0[6], sel, 1'b1);
MUX4to1_1bit m7(input0[7], input1[7], input2[7], input3[7], output0[7], sel, 1'b1);



endmodule

module MUX4to1_32bit(
  input0,
  input1,
  input2,
  input3,
  output0,
  sel
);

input [31:0]input0, input1, input2, input3;
input [1:0]sel;
output [31:0]output0;

MUX4to1_8bit m0(input0[7:0], input1[7:0], input2[7:0], input3[7:0], output0[7:0], sel);
MUX4to1_8bit m1(input0[15:8], input1[15:8], input2[15:8], input3[15:8], output0[15:8], sel);
MUX4to1_8bit m2(input0[23:16], input1[23:16], input2[23:16], input3[23:16], output0[23:16], sel);
MUX4to1_8bit m3(input0[31:24], input1[31:24], input2[31:24], input3[31:24], output0[31:24], sel);

endmodule

module MUX8to1_1bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  output0,
  sel,
  on
);

input input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7;
input [2:0]sel;
input on;
output output0;


wire [1:0]w1;
wire [1:0]on1;
and a0(on1[0], ~sel[2], on);
and a1(on1[1], sel[2], on);

MUX4to1_1bit m0(input0, input1, input2, input3, w1[0], sel[1:0], on1[0]);
MUX4to1_1bit m1(input4, input5, input6, input7, w1[1], sel[1:0], on1[1]);

or o1(output0, w1[0], w1[1]);

endmodule

module MUX8to1_8bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  output0,
  sel
);

input [7:0]input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7;
input [2:0]sel;
output [7:0]output0;

MUX8to1_1bit m0(input0[0], input1[0], input2[0], input3[0], input4[0], input5[0], input6[0], input7[0], output0[0], sel, 1'b1);
MUX8to1_1bit m1(input0[1], input1[1], input2[1], input3[1], input4[1], input5[1], input6[1], input7[1], output0[1], sel, 1'b1);
MUX8to1_1bit m2(input0[2], input1[2], input2[2], input3[2], input4[2], input5[2], input6[2], input7[2], output0[2], sel, 1'b1);
MUX8to1_1bit m3(input0[3], input1[3], input2[3], input3[3], input4[3], input5[3], input6[3], input7[3], output0[3], sel, 1'b1);
MUX8to1_1bit m4(input0[4], input1[4], input2[4], input3[4], input4[4], input5[4], input6[4], input7[4], output0[4], sel, 1'b1);
MUX8to1_1bit m5(input0[5], input1[5], input2[5], input3[5], input4[5], input5[5], input6[5], input7[5], output0[5], sel, 1'b1);
MUX8to1_1bit m6(input0[6], input1[6], input2[6], input3[6], input4[6], input5[6], input6[6], input7[6], output0[6], sel, 1'b1);
MUX8to1_1bit m7(input0[7], input1[7], input2[7], input3[7], input4[7], input5[7], input6[7], input7[7], output0[7], sel, 1'b1);

endmodule

module MUX16to1_1bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  input8,
  input9,
  input10,
  input11,
  input12,
  input13,
  input14,
  input15,
  output0,
  sel,
  on
);

input input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7,
      input8,
      input9,
      input10,
      input11,
      input12,
      input13,
      input14,
      input15;
input [3:0]sel;
input on;
output output0;

wire [1:0]w1;
wire [1:0]on1;
and a0(on1[0], ~sel[3], on);
and a1(on1[1], sel[3], on);

MUX8to1_1bit m0(input0, input1, input2, input3, input4, input5, input6, input7, w1[0], sel[2:0], on1[0]);
MUX8to1_1bit m1(input8, input9, input10, input11, input12, input13, input14, input15, w1[1], sel[2:0], on1[1]);

or o1(output0, w1[0], w1[1]);

endmodule

module MUX32to1_1bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  input8,
  input9,
  input10,
  input11,
  input12,
  input13,
  input14,
  input15,
  input16,
  input17,
  input18,
  input19,
  input20,
  input21,
  input22,
  input23,
  input24,
  input25,
  input26,
  input27,
  input28,
  input29,
  input30,
  input31,
  output0,
  sel,
  on
);

input input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7,
      input8,
      input9,
      input10,
      input11,
      input12,
      input13,
      input14,
      input15,
      input16,
      input17,
      input18,
      input19,
      input20,
      input21,
      input22,
      input23,
      input24,
      input25,
      input26,
      input27,
      input28,
      input29,
      input30,
      input31;
input [4:0]sel;
input on;
output output0;

wire [1:0]w1;
wire [1:0]on1;
and a0(on1[0], ~sel[4], on);
and a1(on1[1], sel[4], on);

MUX16to1_1bit m0(input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, w1[0], sel[3:0], on1[0]);
MUX16to1_1bit m1(input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, w1[1], sel[3:0], on1[1]);

or o1(output0, w1[0], w1[1]);

endmodule

module MUX32to1_8bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  input8,
  input9,
  input10,
  input11,
  input12,
  input13,
  input14,
  input15,
  input16,
  input17,
  input18,
  input19,
  input20,
  input21,
  input22,
  input23,
  input24,
  input25,
  input26,
  input27,
  input28,
  input29,
  input30,
  input31,
  output1,
  sel
);

input [7:0]input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7,
      input8,
      input9,
      input10,
      input11,
      input12,
      input13,
      input14,
      input15,
      input16,
      input17,
      input18,
      input19,
      input20,
      input21,
      input22,
      input23,
      input24,
      input25,
      input26,
      input27,
      input28,
      input29,
      input30,
      input31;
input [4:0]sel;
output [7:0]output1;


MUX32to1_1bit m0(input0[0], input1[0], input2[0], input3[0], input4[0], input5[0], input6[0], input7[0], input8[0], input9[0], input10[0], input11[0], input12[0], input13[0], input14[0], input15[0], input16[0], input17[0], input18[0], input19[0], input20[0], input21[0], input22[0], input23[0], input24[0], input25[0], input26[0], input27[0], input28[0], input29[0], input30[0], input31[0], output1[0], sel, 1'b1);
MUX32to1_1bit m1(input0[1], input1[1], input2[1], input3[1], input4[1], input5[1], input6[1], input7[1], input8[1], input9[1], input10[1], input11[1], input12[1], input13[1], input14[1], input15[1], input16[1], input17[1], input18[1], input19[1], input20[1], input21[1], input22[1], input23[1], input24[1], input25[1], input26[1], input27[1], input28[1], input29[1], input30[1], input31[1], output1[1], sel, 1'b1);
MUX32to1_1bit m2(input0[2], input1[2], input2[2], input3[2], input4[2], input5[2], input6[2], input7[2], input8[2], input9[2], input10[2], input11[2], input12[2], input13[2], input14[2], input15[2], input16[2], input17[2], input18[2], input19[2], input20[2], input21[2], input22[2], input23[2], input24[2], input25[2], input26[2], input27[2], input28[2], input29[2], input30[2], input31[2], output1[2], sel, 1'b1);
MUX32to1_1bit m3(input0[3], input1[3], input2[3], input3[3], input4[3], input5[3], input6[3], input7[3], input8[3], input9[3], input10[3], input11[3], input12[3], input13[3], input14[3], input15[3], input16[3], input17[3], input18[3], input19[3], input20[3], input21[3], input22[3], input23[3], input24[3], input25[3], input26[3], input27[3], input28[3], input29[3], input30[3], input31[3], output1[3], sel, 1'b1);
MUX32to1_1bit m4(input0[4], input1[4], input2[4], input3[4], input4[4], input5[4], input6[4], input7[4], input8[4], input9[4], input10[4], input11[4], input12[4], input13[4], input14[4], input15[4], input16[4], input17[4], input18[4], input19[4], input20[4], input21[4], input22[4], input23[4], input24[4], input25[4], input26[4], input27[4], input28[4], input29[4], input30[4], input31[4], output1[4], sel, 1'b1);
MUX32to1_1bit m5(input0[5], input1[5], input2[5], input3[5], input4[5], input5[5], input6[5], input7[5], input8[5], input9[5], input10[5], input11[5], input12[5], input13[5], input14[5], input15[5], input16[5], input17[5], input18[5], input19[5], input20[5], input21[5], input22[5], input23[5], input24[5], input25[5], input26[5], input27[5], input28[5], input29[5], input30[5], input31[5], output1[5], sel, 1'b1);
MUX32to1_1bit m6(input0[6], input1[6], input2[6], input3[6], input4[6], input5[6], input6[6], input7[6], input8[6], input9[6], input10[6], input11[6], input12[6], input13[6], input14[6], input15[6], input16[6], input17[6], input18[6], input19[6], input20[6], input21[6], input22[6], input23[6], input24[6], input25[6], input26[6], input27[6], input28[6], input29[6], input30[6], input31[6], output1[6], sel, 1'b1);
MUX32to1_1bit m7(input0[7], input1[7], input2[7], input3[7], input4[7], input5[7], input6[7], input7[7], input8[7], input9[7], input10[7], input11[7], input12[7], input13[7], input14[7], input15[7], input16[7], input17[7], input18[7], input19[7], input20[7], input21[7], input22[7], input23[7], input24[7], input25[7], input26[7], input27[7], input28[7], input29[7], input30[7], input31[7], output1[7], sel, 1'b1);



endmodule

module MUX32to1_32bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  input8,
  input9,
  input10,
  input11,
  input12,
  input13,
  input14,
  input15,
  input16,
  input17,
  input18,
  input19,
  input20,
  input21,
  input22,
  input23,
  input24,
  input25,
  input26,
  input27,
  input28,
  input29,
  input30,
  input31,
  output1,
  sel
);

input [31:0]input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7,
      input8,
      input9,
      input10,
      input11,
      input12,
      input13,
      input14,
      input15,
      input16,
      input17,
      input18,
      input19,
      input20,
      input21,
      input22,
      input23,
      input24,
      input25,
      input26,
      input27,
      input28,
      input29,
      input30,
      input31;
input [4:0]sel;
output [31:0]output1;

MUX32to1_1bit m0(input0[0], input1[0], input2[0], input3[0], input4[0], input5[0], input6[0], input7[0], input8[0], input9[0], input10[0], input11[0], input12[0], input13[0], input14[0], input15[0], input16[0], input17[0], input18[0], input19[0], input20[0], input21[0], input22[0], input23[0], input24[0], input25[0], input26[0], input27[0], input28[0], input29[0], input30[0], input31[0], output1[0], sel, 1'b1);
MUX32to1_1bit m1(input0[1], input1[1], input2[1], input3[1], input4[1], input5[1], input6[1], input7[1], input8[1], input9[1], input10[1], input11[1], input12[1], input13[1], input14[1], input15[1], input16[1], input17[1], input18[1], input19[1], input20[1], input21[1], input22[1], input23[1], input24[1], input25[1], input26[1], input27[1], input28[1], input29[1], input30[1], input31[1], output1[1], sel, 1'b1);
MUX32to1_1bit m2(input0[2], input1[2], input2[2], input3[2], input4[2], input5[2], input6[2], input7[2], input8[2], input9[2], input10[2], input11[2], input12[2], input13[2], input14[2], input15[2], input16[2], input17[2], input18[2], input19[2], input20[2], input21[2], input22[2], input23[2], input24[2], input25[2], input26[2], input27[2], input28[2], input29[2], input30[2], input31[2], output1[2], sel, 1'b1);
MUX32to1_1bit m3(input0[3], input1[3], input2[3], input3[3], input4[3], input5[3], input6[3], input7[3], input8[3], input9[3], input10[3], input11[3], input12[3], input13[3], input14[3], input15[3], input16[3], input17[3], input18[3], input19[3], input20[3], input21[3], input22[3], input23[3], input24[3], input25[3], input26[3], input27[3], input28[3], input29[3], input30[3], input31[3], output1[3], sel, 1'b1);
MUX32to1_1bit m4(input0[4], input1[4], input2[4], input3[4], input4[4], input5[4], input6[4], input7[4], input8[4], input9[4], input10[4], input11[4], input12[4], input13[4], input14[4], input15[4], input16[4], input17[4], input18[4], input19[4], input20[4], input21[4], input22[4], input23[4], input24[4], input25[4], input26[4], input27[4], input28[4], input29[4], input30[4], input31[4], output1[4], sel, 1'b1);
MUX32to1_1bit m5(input0[5], input1[5], input2[5], input3[5], input4[5], input5[5], input6[5], input7[5], input8[5], input9[5], input10[5], input11[5], input12[5], input13[5], input14[5], input15[5], input16[5], input17[5], input18[5], input19[5], input20[5], input21[5], input22[5], input23[5], input24[5], input25[5], input26[5], input27[5], input28[5], input29[5], input30[5], input31[5], output1[5], sel, 1'b1);
MUX32to1_1bit m6(input0[6], input1[6], input2[6], input3[6], input4[6], input5[6], input6[6], input7[6], input8[6], input9[6], input10[6], input11[6], input12[6], input13[6], input14[6], input15[6], input16[6], input17[6], input18[6], input19[6], input20[6], input21[6], input22[6], input23[6], input24[6], input25[6], input26[6], input27[6], input28[6], input29[6], input30[6], input31[6], output1[6], sel, 1'b1);
MUX32to1_1bit m7(input0[7], input1[7], input2[7], input3[7], input4[7], input5[7], input6[7], input7[7], input8[7], input9[7], input10[7], input11[7], input12[7], input13[7], input14[7], input15[7], input16[7], input17[7], input18[7], input19[7], input20[7], input21[7], input22[7], input23[7], input24[7], input25[7], input26[7], input27[7], input28[7], input29[7], input30[7], input31[7], output1[7], sel, 1'b1);
MUX32to1_1bit m8(input0[8], input1[8], input2[8], input3[8], input4[8], input5[8], input6[8], input7[8], input8[8], input9[8], input10[8], input11[8], input12[8], input13[8], input14[8], input15[8], input16[8], input17[8], input18[8], input19[8], input20[8], input21[8], input22[8], input23[8], input24[8], input25[8], input26[8], input27[8], input28[8], input29[8], input30[8], input31[8], output1[8], sel, 1'b1);
MUX32to1_1bit m9(input0[9], input1[9], input2[9], input3[9], input4[9], input5[9], input6[9], input7[9], input8[9], input9[9], input10[9], input11[9], input12[9], input13[9], input14[9], input15[9], input16[9], input17[9], input18[9], input19[9], input20[9], input21[9], input22[9], input23[9], input24[9], input25[9], input26[9], input27[9], input28[9], input29[9], input30[9], input31[9], output1[9], sel, 1'b1);
MUX32to1_1bit m10(input0[10], input1[10], input2[10], input3[10], input4[10], input5[10], input6[10], input7[10], input8[10], input9[10], input10[10], input11[10], input12[10], input13[10], input14[10], input15[10], input16[10], input17[10], input18[10], input19[10], input20[10], input21[10], input22[10], input23[10], input24[10], input25[10], input26[10], input27[10], input28[10], input29[10], input30[10], input31[10], output1[10], sel, 1'b1);
MUX32to1_1bit m11(input0[11], input1[11], input2[11], input3[11], input4[11], input5[11], input6[11], input7[11], input8[11], input9[11], input10[11], input11[11], input12[11], input13[11], input14[11], input15[11], input16[11], input17[11], input18[11], input19[11], input20[11], input21[11], input22[11], input23[11], input24[11], input25[11], input26[11], input27[11], input28[11], input29[11], input30[11], input31[11], output1[11], sel, 1'b1);
MUX32to1_1bit m12(input0[12], input1[12], input2[12], input3[12], input4[12], input5[12], input6[12], input7[12], input8[12], input9[12], input10[12], input11[12], input12[12], input13[12], input14[12], input15[12], input16[12], input17[12], input18[12], input19[12], input20[12], input21[12], input22[12], input23[12], input24[12], input25[12], input26[12], input27[12], input28[12], input29[12], input30[12], input31[12], output1[12], sel, 1'b1);
MUX32to1_1bit m13(input0[13], input1[13], input2[13], input3[13], input4[13], input5[13], input6[13], input7[13], input8[13], input9[13], input10[13], input11[13], input12[13], input13[13], input14[13], input15[13], input16[13], input17[13], input18[13], input19[13], input20[13], input21[13], input22[13], input23[13], input24[13], input25[13], input26[13], input27[13], input28[13], input29[13], input30[13], input31[13], output1[13], sel, 1'b1);
MUX32to1_1bit m14(input0[14], input1[14], input2[14], input3[14], input4[14], input5[14], input6[14], input7[14], input8[14], input9[14], input10[14], input11[14], input12[14], input13[14], input14[14], input15[14], input16[14], input17[14], input18[14], input19[14], input20[14], input21[14], input22[14], input23[14], input24[14], input25[14], input26[14], input27[14], input28[14], input29[14], input30[14], input31[14], output1[14], sel, 1'b1);
MUX32to1_1bit m15(input0[15], input1[15], input2[15], input3[15], input4[15], input5[15], input6[15], input7[15], input8[15], input9[15], input10[15], input11[15], input12[15], input13[15], input14[15], input15[15], input16[15], input17[15], input18[15], input19[15], input20[15], input21[15], input22[15], input23[15], input24[15], input25[15], input26[15], input27[15], input28[15], input29[15], input30[15], input31[15], output1[15], sel, 1'b1);
MUX32to1_1bit m16(input0[16], input1[16], input2[16], input3[16], input4[16], input5[16], input6[16], input7[16], input8[16], input9[16], input10[16], input11[16], input12[16], input13[16], input14[16], input15[16], input16[16], input17[16], input18[16], input19[16], input20[16], input21[16], input22[16], input23[16], input24[16], input25[16], input26[16], input27[16], input28[16], input29[16], input30[16], input31[16], output1[16], sel, 1'b1);
MUX32to1_1bit m17(input0[17], input1[17], input2[17], input3[17], input4[17], input5[17], input6[17], input7[17], input8[17], input9[17], input10[17], input11[17], input12[17], input13[17], input14[17], input15[17], input16[17], input17[17], input18[17], input19[17], input20[17], input21[17], input22[17], input23[17], input24[17], input25[17], input26[17], input27[17], input28[17], input29[17], input30[17], input31[17], output1[17], sel, 1'b1);
MUX32to1_1bit m18(input0[18], input1[18], input2[18], input3[18], input4[18], input5[18], input6[18], input7[18], input8[18], input9[18], input10[18], input11[18], input12[18], input13[18], input14[18], input15[18], input16[18], input17[18], input18[18], input19[18], input20[18], input21[18], input22[18], input23[18], input24[18], input25[18], input26[18], input27[18], input28[18], input29[18], input30[18], input31[18], output1[18], sel, 1'b1);
MUX32to1_1bit m19(input0[19], input1[19], input2[19], input3[19], input4[19], input5[19], input6[19], input7[19], input8[19], input9[19], input10[19], input11[19], input12[19], input13[19], input14[19], input15[19], input16[19], input17[19], input18[19], input19[19], input20[19], input21[19], input22[19], input23[19], input24[19], input25[19], input26[19], input27[19], input28[19], input29[19], input30[19], input31[19], output1[19], sel, 1'b1);
MUX32to1_1bit m20(input0[20], input1[20], input2[20], input3[20], input4[20], input5[20], input6[20], input7[20], input8[20], input9[20], input10[20], input11[20], input12[20], input13[20], input14[20], input15[20], input16[20], input17[20], input18[20], input19[20], input20[20], input21[20], input22[20], input23[20], input24[20], input25[20], input26[20], input27[20], input28[20], input29[20], input30[20], input31[20], output1[20], sel, 1'b1);
MUX32to1_1bit m21(input0[21], input1[21], input2[21], input3[21], input4[21], input5[21], input6[21], input7[21], input8[21], input9[21], input10[21], input11[21], input12[21], input13[21], input14[21], input15[21], input16[21], input17[21], input18[21], input19[21], input20[21], input21[21], input22[21], input23[21], input24[21], input25[21], input26[21], input27[21], input28[21], input29[21], input30[21], input31[21], output1[21], sel, 1'b1);
MUX32to1_1bit m22(input0[22], input1[22], input2[22], input3[22], input4[22], input5[22], input6[22], input7[22], input8[22], input9[22], input10[22], input11[22], input12[22], input13[22], input14[22], input15[22], input16[22], input17[22], input18[22], input19[22], input20[22], input21[22], input22[22], input23[22], input24[22], input25[22], input26[22], input27[22], input28[22], input29[22], input30[22], input31[22], output1[22], sel, 1'b1);
MUX32to1_1bit m23(input0[23], input1[23], input2[23], input3[23], input4[23], input5[23], input6[23], input7[23], input8[23], input9[23], input10[23], input11[23], input12[23], input13[23], input14[23], input15[23], input16[23], input17[23], input18[23], input19[23], input20[23], input21[23], input22[23], input23[23], input24[23], input25[23], input26[23], input27[23], input28[23], input29[23], input30[23], input31[23], output1[23], sel, 1'b1);
MUX32to1_1bit m24(input0[24], input1[24], input2[24], input3[24], input4[24], input5[24], input6[24], input7[24], input8[24], input9[24], input10[24], input11[24], input12[24], input13[24], input14[24], input15[24], input16[24], input17[24], input18[24], input19[24], input20[24], input21[24], input22[24], input23[24], input24[24], input25[24], input26[24], input27[24], input28[24], input29[24], input30[24], input31[24], output1[24], sel, 1'b1);
MUX32to1_1bit m25(input0[25], input1[25], input2[25], input3[25], input4[25], input5[25], input6[25], input7[25], input8[25], input9[25], input10[25], input11[25], input12[25], input13[25], input14[25], input15[25], input16[25], input17[25], input18[25], input19[25], input20[25], input21[25], input22[25], input23[25], input24[25], input25[25], input26[25], input27[25], input28[25], input29[25], input30[25], input31[25], output1[25], sel, 1'b1);
MUX32to1_1bit m26(input0[26], input1[26], input2[26], input3[26], input4[26], input5[26], input6[26], input7[26], input8[26], input9[26], input10[26], input11[26], input12[26], input13[26], input14[26], input15[26], input16[26], input17[26], input18[26], input19[26], input20[26], input21[26], input22[26], input23[26], input24[26], input25[26], input26[26], input27[26], input28[26], input29[26], input30[26], input31[26], output1[26], sel, 1'b1);
MUX32to1_1bit m27(input0[27], input1[27], input2[27], input3[27], input4[27], input5[27], input6[27], input7[27], input8[27], input9[27], input10[27], input11[27], input12[27], input13[27], input14[27], input15[27], input16[27], input17[27], input18[27], input19[27], input20[27], input21[27], input22[27], input23[27], input24[27], input25[27], input26[27], input27[27], input28[27], input29[27], input30[27], input31[27], output1[27], sel, 1'b1);
MUX32to1_1bit m28(input0[28], input1[28], input2[28], input3[28], input4[28], input5[28], input6[28], input7[28], input8[28], input9[28], input10[28], input11[28], input12[28], input13[28], input14[28], input15[28], input16[28], input17[28], input18[28], input19[28], input20[28], input21[28], input22[28], input23[28], input24[28], input25[28], input26[28], input27[28], input28[28], input29[28], input30[28], input31[28], output1[28], sel, 1'b1);
MUX32to1_1bit m29(input0[29], input1[29], input2[29], input3[29], input4[29], input5[29], input6[29], input7[29], input8[29], input9[29], input10[29], input11[29], input12[29], input13[29], input14[29], input15[29], input16[29], input17[29], input18[29], input19[29], input20[29], input21[29], input22[29], input23[29], input24[29], input25[29], input26[29], input27[29], input28[29], input29[29], input30[29], input31[29], output1[29], sel, 1'b1);
MUX32to1_1bit m30(input0[30], input1[30], input2[30], input3[30], input4[30], input5[30], input6[30], input7[30], input8[30], input9[30], input10[30], input11[30], input12[30], input13[30], input14[30], input15[30], input16[30], input17[30], input18[30], input19[30], input20[30], input21[30], input22[30], input23[30], input24[30], input25[30], input26[30], input27[30], input28[30], input29[30], input30[30], input31[30], output1[30], sel, 1'b1);
MUX32to1_1bit m31(input0[31], input1[31], input2[31], input3[31], input4[31], input5[31], input6[31], input7[31], input8[31], input9[31], input10[31], input11[31], input12[31], input13[31], input14[31], input15[31], input16[31], input17[31], input18[31], input19[31], input20[31], input21[31], input22[31], input23[31], input24[31], input25[31], input26[31], input27[31], input28[31], input29[31], input30[31], input31[31], output1[31], sel, 1'b1);



endmodule

//MUX END

//FlipFlop and Register START

module dflipflop(
  clk,
  rst, 
  input1,
  output1,
  noutput1
);

input input1, clk, rst;
output output1, noutput1;

wire w1, w2, w3, w4;
wire  input2;
and a1(input2, input1, rst);

nand n1(w1, w4, w2);
nand n2(w2, w1, clk);
nand n3(w3, w2, clk, w4);
nand n4(w4, w3, input2);

nand n5(output1, w2, noutput1);
nand n6(noutput1, output1, w3);


endmodule

module Register_8bit(
  clk,
  rst,
  d,
  q,
  sel
 );
  
  input clk, rst;
  input [7:0]d;
  input [1:0]sel; // 00:no change, 01:right shift, 10:left shift, 11:input
  output [7:0]q;
  
  wire [7:0]dd;
  wire [7:0]nq;
  
  dflipflop d1(clk, rst, dd[0], q[0], nq[0]);
  dflipflop d2(clk, rst, dd[1], q[1], nq[1]);
  dflipflop d3(clk, rst, dd[2], q[2], nq[2]);
  dflipflop d4(clk, rst, dd[3], q[3], nq[3]);
  dflipflop d5(clk, rst, dd[4], q[4], nq[4]);
  dflipflop d6(clk, rst, dd[5], q[5], nq[5]);
  dflipflop d7(clk, rst, dd[6], q[6], nq[6]);
  dflipflop d8(clk, rst, dd[7], q[7], nq[7]);
  
  MUX4to1_8bit m0(q, {q[0],q[7:1]}, {q[6:0],q[7]}, d, dd, sel);
  
endmodule

module Register_32bit(
  clk,
  rst,
  d,
  q,
  sel
);

input clk, rst;
input [31:0]d;
input [1:0]sel; // 00:no change, 01:right shift, 10:left shift, 11:input
output [31:0]q;

wire [31:0]dd;
Register_8bit rg0(clk, rst, dd[7:0], q[7:0], 2'b11);
Register_8bit rg1(clk, rst, dd[15:8], q[15:8], 2'b11);
Register_8bit rg2(clk, rst, dd[23:16], q[23:16], 2'b11);
Register_8bit rg3(clk, rst, dd[31:24], q[31:24], 2'b11);


MUX4to1_32bit m0(q, {q[0], q[31:1]}, {q[30:0], q[31]}, d, dd, sel);

endmodule


//FlipFlop and Register END

//Decoder START
module DEC5to32(in, out);
input [4:0] in;
output [31:0] out;
wire [15:0] DecodedData;
wire Nin;


assign Nin = ~in[4];
DEC4to16 Dec4(in[3:0], DecodedData[15:0]);

and(out[31], in[4], DecodedData[15]);
and(out[30], in[4], DecodedData[14]);
and(out[29], in[4], DecodedData[13]);
and(out[28], in[4], DecodedData[12]);
and(out[27], in[4], DecodedData[11]);
and(out[26], in[4], DecodedData[10]);
and(out[25], in[4], DecodedData[9]);
and(out[24], in[4], DecodedData[8]);
and(out[23], in[4], DecodedData[7]);
and(out[22], in[4], DecodedData[6]);
and(out[21], in[4], DecodedData[5]);
and(out[20], in[4], DecodedData[4]);
and(out[19], in[4], DecodedData[3]);
and(out[18], in[4], DecodedData[2]);
and(out[17], in[4], DecodedData[1]);
and(out[16], in[4], DecodedData[0]);

and(out[15], Nin, DecodedData[15]);
and(out[14], Nin, DecodedData[14]);
and(out[13], Nin, DecodedData[13]);
and(out[12], Nin, DecodedData[12]);
and(out[11], Nin, DecodedData[11]);
and(out[10], Nin, DecodedData[10]);
and(out[9], Nin, DecodedData[9]);
and(out[8], Nin, DecodedData[8]);
and(out[7], Nin, DecodedData[7]);
and(out[6], Nin, DecodedData[6]);
and(out[5], Nin, DecodedData[5]);
and(out[4], Nin, DecodedData[4]);
and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);

endmodule


module DEC4to16(in, out);
input [3:0] in;
output [15:0] out;
wire [7:0] DecodedData;
wire Nin;

assign Nin = ~in[3];
DEC3to8 Dec3(in[2:0], DecodedData[7:0]);

and(out[15], in[3], DecodedData[7]);
and(out[14], in[3], DecodedData[6]);
and(out[13], in[3], DecodedData[5]);
and(out[12], in[3], DecodedData[4]);
and(out[11], in[3], DecodedData[3]);
and(out[10], in[3], DecodedData[2]);
and(out[9], in[3], DecodedData[1]);
and(out[8], in[3], DecodedData[0]);

and(out[7], Nin, DecodedData[7]);
and(out[6], Nin, DecodedData[6]);
and(out[5], Nin, DecodedData[5]);
and(out[4], Nin, DecodedData[4]);
and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);


endmodule


module DEC3to8(in, out);
input [2:0] in;
output [7:0] out;
wire [3:0] DecodedData;
wire Nin;
assign Nin = ~in[2];
DEC2to4 Dec2(in[1:0], DecodedData[3:0]);


and(out[7], in[2], DecodedData[3]);
and(out[6], in[2], DecodedData[2]);
and(out[5], in[2], DecodedData[1]);
and(out[4], in[2], DecodedData[0]);


and(out[3], Nin, DecodedData[3]);
and(out[2], Nin, DecodedData[2]);
and(out[1], Nin, DecodedData[1]);
and(out[0], Nin, DecodedData[0]);

endmodule

module DEC2to4(in, out);
input [1:0] in;
output [3:0] out;
wire [1:0] Nin;

assign Nin = ~in;

and a1(out[0], Nin[1], Nin[0]);
and a2(out[1], Nin[1], in[0]);
and a3(out[2], in[1], Nin[0]);
and a4(out[3], in[1], in[0]);

endmodule

//Decoder END

//Adder and Subtracter START

module Halfadder(
	input1,
	input2,
	sum,
	carryout
);

input input1, input2;
output sum, carryout;

xor x1(sum, input1, input2);
and a1(carryout, input1, input2);

endmodule

module Fulladder(
	input1,
	input2,
	carryin,
	sum,
	carryout
);

input input1, input2, carryin;
output sum, carryout;

wire w1, w2, w3;

Halfadder h1(input1, input2, w1, w2);
Halfadder h2(w1, carryin, sum, w3);
or o1(carryout, w3, w2);

endmodule

module Adder_32bit(
  input1, 
  input2, 
  sum
);

input [31:0]input1, input2;
output [31:0]sum;

wire [31:0]carryout;

Fulladder fa0(input1[0], input2[0], 1'b0, sum[0], carryout[0]);
Fulladder fa1(input1[1], input2[1], carryout[0], sum[1], carryout[1]);
Fulladder fa2(input1[2], input2[2], carryout[1], sum[2], carryout[2]);
Fulladder fa3(input1[3], input2[3], carryout[2], sum[3], carryout[3]);
Fulladder fa4(input1[4], input2[4], carryout[3], sum[4], carryout[4]);
Fulladder fa5(input1[5], input2[5], carryout[4], sum[5], carryout[5]);
Fulladder fa6(input1[6], input2[6], carryout[5], sum[6], carryout[6]);
Fulladder fa7(input1[7], input2[7], carryout[6], sum[7], carryout[7]);
Fulladder fa8(input1[8], input2[8], carryout[7], sum[8], carryout[8]);
Fulladder fa9(input1[9], input2[9], carryout[8], sum[9], carryout[9]);
Fulladder fa10(input1[10], input2[10], carryout[9], sum[10], carryout[10]);
Fulladder fa11(input1[11], input2[11], carryout[10], sum[11], carryout[11]);
Fulladder fa12(input1[12], input2[12], carryout[11], sum[12], carryout[12]);
Fulladder fa13(input1[13], input2[13], carryout[12], sum[13], carryout[13]);
Fulladder fa14(input1[14], input2[14], carryout[13], sum[14], carryout[14]);
Fulladder fa15(input1[15], input2[15], carryout[14], sum[15], carryout[15]);
Fulladder fa16(input1[16], input2[16], carryout[15], sum[16], carryout[16]);
Fulladder fa17(input1[17], input2[17], carryout[16], sum[17], carryout[17]);
Fulladder fa18(input1[18], input2[18], carryout[17], sum[18], carryout[18]);
Fulladder fa19(input1[19], input2[19], carryout[18], sum[19], carryout[19]);
Fulladder fa20(input1[20], input2[20], carryout[19], sum[20], carryout[20]);
Fulladder fa21(input1[21], input2[21], carryout[20], sum[21], carryout[21]);
Fulladder fa22(input1[22], input2[22], carryout[21], sum[22], carryout[22]);
Fulladder fa23(input1[23], input2[23], carryout[22], sum[23], carryout[23]);
Fulladder fa24(input1[24], input2[24], carryout[23], sum[24], carryout[24]);
Fulladder fa25(input1[25], input2[25], carryout[24], sum[25], carryout[25]);
Fulladder fa26(input1[26], input2[26], carryout[25], sum[26], carryout[26]);
Fulladder fa27(input1[27], input2[27], carryout[26], sum[27], carryout[27]);
Fulladder fa28(input1[28], input2[28], carryout[27], sum[28], carryout[28]);
Fulladder fa29(input1[29], input2[29], carryout[28], sum[29], carryout[29]);
Fulladder fa30(input1[30], input2[30], carryout[29], sum[30], carryout[30]);
Fulladder fa31(input1[31], input2[31], carryout[30], sum[31], carryout[31]);

endmodule
  

module AdderSubtracter(
  input1,
  input2,
  sum,
  overflow,
  carryout,
  opcode
);

input [7:0]input1;
input [7:0]input2;
input opcode; //if opcode=0; adder, elseif opcode=1; subtracter
output [7:0]sum;
output overflow;
output carryout;

wire [7:0]input21;
wire [6:0]carry;

xor o0(input21[0], input2[0], opcode);
xor o1(input21[1], input2[1], opcode);
xor o2(input21[2], input2[2], opcode);
xor o3(input21[3], input2[3], opcode);
xor o4(input21[4], input2[4], opcode);
xor o5(input21[5], input2[5], opcode);
xor o6(input21[6], input2[6], opcode);
xor o7(input21[7], input2[7], opcode);

Fulladder f1(input1[0], input21[0], opcode, sum[0], carry[0]);
Fulladder f2(input1[1], input21[1], carry[0], sum[1], carry[1]);
Fulladder f3(input1[2], input21[2], carry[1], sum[2], carry[2]);
Fulladder f4(input1[3], input21[3], carry[2], sum[3], carry[3]);
Fulladder f5(input1[4], input21[4], carry[3], sum[4], carry[4]);
Fulladder f6(input1[5], input21[5], carry[4], sum[5], carry[5]);
Fulladder f7(input1[6], input21[6], carry[5], sum[6], carry[6]);
Fulladder f8(input1[7], input21[7], carry[6], sum[7], carryout);

xor o8(overflow, carryout, carry[6]);

endmodule

module Slt(A, B, Out);
  input [7:0] A, B;
  output [7:0] Out;
  wire [7:0] wS;
  
  wire overflow, carryin;
  AdderSubtracter S1(A, B, wS, overflow, carryin, 1'b1);
  
  
  wire [7:0]Out1, Out2;
  and out10(Out1[0], 1'b0, wS[7]);
  and out11(Out1[0], 1'b0, wS[7]);
  and out12(Out1[0], 1'b0, wS[7]);
  and out13(Out1[0], 1'b0, wS[7]);
  and out14(Out1[0], 1'b0, wS[7]);
  and out15(Out1[0], 1'b0, wS[7]);
  and out16(Out1[0], 1'b0, wS[7]);
  and out17(Out1[0], 1'b0, wS[7]);
 
  and out20(Out2[0], 1'b1, wS[7]);
  and out21(Out2[0], 1'b0, wS[7]);
  and out22(Out2[0], 1'b0, wS[7]);
  and out23(Out2[0], 1'b0, wS[7]);
  and out24(Out2[0], 1'b0, wS[7]);
  and out25(Out2[0], 1'b0, wS[7]);
  and out26(Out2[0], 1'b0, wS[7]);
  and out27(Out2[0], 1'b0, wS[7]);
  
  or out30(Out[0], Out1[0], Out2[0]);
  or out31(Out[1], Out1[1], Out2[1]);
  or out32(Out[2], Out1[2], Out2[2]);
  or out33(Out[3], Out1[3], Out2[3]);
  or out34(Out[4], Out1[4], Out2[4]);
  or out35(Out[5], Out1[5], Out2[5]);
  or out36(Out[6], Out1[6], Out2[6]);
  or out37(Out[7], Out1[7], Out2[7]);
  
endmodule

//Adder and Subtracter END